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Whitepapers, datasheets, and application notes to support your design decisions.
Datasheet
PCIeIP Core
PCIe Gen 5 Controller IP — Product Brief
Silicon-proven PCIe Gen 5 (32 GT/s) controller IP supporting x1 to x16 link widths, LTSSM, SR-IOV, and AXI4 host interface. Available for TSMC 7nm and below.
2024-01-202.1 MB
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