Knowledge Base
Engineering Blog
Deep dives into ASIC design, FPGA development, verification methodology, and silicon engineering from our team.
UVMVerification
UVM Testbench Best Practices for Complex ASIC Designs
A deep dive into structuring scalable UVM testbenches — from agent architecture to coverage closure strategies for complex SoC designs.
2024-03-0112 min read
ASICPower
Power Optimization in Deep-Submicron ASICs: From RTL to GDSII
How we achieve aggressive PPA targets through multi-stage power optimization — clock gating at RTL, power domains in synthesis, and fine-grain analysis in physical design.
2024-02-1410 min read